What is R5F562TADDFF?

This is 100-MHz 32-bit RX MCUs.

[PDF] Complete Technical Details can be found in the R5F562TADDFF datasheet provided at this page.

Summary in PDF File

DATASHEET RX62T Group RX62G Group Renesas MCUs R01DS0096EJ0200 100 MHz 32 bit RX MCUs FPU 165 DMIPS 12 bit ADC 3 S H circuits double data register amplifier comparator two units 10 bit ADC one unit the three ADC units are Rev 2 00 Jan 10 2014 capable of simultaneous 7 ch sampling 100 MHz PWM two three phase complementary channels and four single phase complementary channels or three three phase complementary channels and one single phase complementary channel Features 32 bit RX CPU core Max operating frequency 100 MHz Capable of 165 DMIPS in operation at 100 MHz Single precision 32 bit IEEE 754 floating point Accumulator handles 64 bit results for a single instruction from 32 32 bit operations Multiplication and division unit handles 32 32 bit operations multiplication instructions take one CPU clock cycle Fast interrupt Divider fastest instruction execution takes two CPU clock cycles Fast interrupt CISC Harvard architecture with 5 stage pipeline Variable length instructions Ultra compact code Supports the memory protection unit MPU Background JTAG debugging plus high speed tracing Operating voltage Single 3 3 or 5 V supply 5 V analog supply is possible with

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Manufacturers : Renesas



100-MHz 32-bit RX MCUs

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