What is HCF4724B?


This is 8 BIT ADDRESSABLE LATCH.


[PDF] Complete Technical Details can be found in the HCF4724B datasheet provided at this page.

Summary in PDF File


HCC4724B HCF4724B 8 BIT ADDRESSABLE LATCH SERIAL DATA INPUT ACTIVE PARALLEL OUTPUT STORAGE REGISTER CAPABILITY MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER STANDARDIZED SYMMETRICAL OUTPUT CHARACTER 100 TESTED FOR QUIESCENT CURRENT AT 20V MAXIMUM INPUT CURRENT OF 1 A AT 18V full package temperature range 100nA AT 18V AND 25oC NOISE MARGIN full package temperature range 1V AT VDD 5V 2V AT VDD 10V 2 5V AT VDD 15V 5V 10V AND 15V PARAMETRIC RATINGS MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N 13A STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES EY Plastic Package F Ceramic Package M1 Micro Package C1 Chip Carrier ORDER CODES HCC4724BF HCF4724BM1 HCF4724BEY HCF4724BC1 APPLICATION MULTI LINE DECODERS A D CONVERTERS PIN CONNECTIONS DESCRIPTION The HCC HCF4724B 8 bit addressable latch is a serial input parallel output storage register that can perform a variety of functions Data are inputted to a particular bit in the latch when that bit is addressed by means of inputs A0 A1 A2 and when WRITE DISABLE is at low level When WRITE DISABLE is high data entry is inhibited however all 8 outputs can be continuously read independent of WRITE DISABLE and address input

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Manufacturers : STMicroelectronics

STM - HCF4724B Datasheet PDF

STM HCF4724B LATCH

8 BIT ADDRESSABLE LATCH

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