What is MC100E154?
This is 5-BIT 2:1 MUX-LATCH. |
[PDF] Complete Technical Details can be found in the
MC100E154 datasheet
provided at this page.Summary in PDF Filewww datasheetgo.com MC10E154 MC100E154 5V ECL 5 Bit 2 1 Mux Latch Description The MC10E 100E154 contains five 2 1 multiplexers followed by transparent latches with differential outputs When both Latch Enables LEN1 LEN2 are LOW the latch is transparent and output data is controlled by the multiplexer select control SEL A logic HIGH on either LEN1 or LEN2 or both latches the outputs The Master Reset MR overrides all other controls to set the Q outputs LOW The 100 Series contains temperature compensation Features http onsemi com 850 ps Maximum LEN to Output 825 ps Maximum D to Output Differential Outputs Asynchronous Master Reset Dual Latch Enables PECL Mode Operating Range VCC 4 2 V to 5 7 V with VEE 0 V NECL Mode Operating Range VCC 0 V with VEE 4 2 V to 5 7 V Internal Input 50 kW Pulldown Resistors ESD Protection Human Body Model 2 kV Machine Model 200 V Meets or Exceeds JEDEC Standard EIA JESD78 IC Latchup Test Moisture Sensitivity Level Pb 1 Pb Free 3 For Additional Information see Application Note AND8003 D Flammability Rating UL 94 V 0 0 125 in Oxygen Index 28 to 34 Transistor Count 237 Devices Pb Free Packages are Available PLCC 2 |
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[ Detailed Data ] |
Manufacturers : ON Semiconductor  |
ONSEMI MC100E154 LATCH 5-BIT 2:1 MUX-LATCH |
Datasheet MC100E154 PDF DownLoad ( ONSEMI ) |