MB84VD21181EM-70 – (MB84VD2118xEM-70 / MB84VD2119xEM-70) Stacked MCP (Multi-Chip Package) FLASH MEMORY

MB84VD21181EM-70 Information is available here.

Part Number : MB84VD21181EM-70

Function : This is a kind of semiconductor, (MB84VD2118xEM-70 / MB84VD2119xEM-70) Stacked MCP (Multi-Chip Package) FLASH MEMORY.

Pinouts :

Package :

Manufacturer : SPANSION

Image :

MB84VD21181EM-70 data sheet

Some text files in PDF file :

FUJITSU SEMICONDUCTOR DATA SHEET DS05-50307-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM 16M (×8/×16) FLASH MEMORY & 4M (×8/×16) STATIC RAM MB84VD2118XEM-70/MB84VD2119XEM-70 s FEATURES • Power Supply Voltage of 2.7 V to 3.3 V • High Performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM) • Operating Temperature –40 °C to +85 °C • Package 56-ball FBGA CMOS (Continued) s PRODUCT LINE-UP Part No. Supply Voltage(V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MB84VD2118XEM/MB84VD2119XEM VCCf*= 3.0 V 70 70 30 +0.3 V –0.3 V VCCs*= 3.0 V +0.3V –0.3 V 70 70 35 *: Both VCCf and VCCs must be in recommended operation range when either part is being accessed. s PACKAGE 56-ball plastic FBGA (BGA-56P-M02) MB84VD2118XEM/2119XEM-70 (Continued) • FLASH MEMORY • Simultaneous Read/Write Operations (Dual Bank) Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Minimum 100,000 Write/Erase Cycles • Sector Erase Architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD2118XEM: Top sector MB84VD2119XEM: Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC Write Inhibi [ … ]

MB84VD21181EM-70 PDF File

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