H5TC4G63AFR-XXA Datasheet PDF learn more.

Part number : H5TC4G63AFR-XXA

Functions : This is a kind of semiconductor, 4Gb DDR3L SDRAM.

Pin arrangement :

Package information :

Manufacturer : SK Hynix

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H5TC4G63AFR-XXA Datasheet PDF

The texts in the PDF file :

4Gb DDR3L SDRAM 4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC4G83AFR-xxA H5TC4G83AFR-xxI H5TC4G83AFR-xxL http:/// H5TC4G83AFR-xxJ H5TC4G63AFR-xxA H5TC4G63AFR-xxI H5TC4G63AFR-xxL H5TC4G63AFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1 / Jan. 2013 1 Revision History Revision No. 1.0 1.1 History Official Version Release x8 IDD update Draft Date Oct. 2012 Jan. 2013 Remark http:/// Rev. 1.1 / Jan. 2013 2


The H5TC4G83AFR-xxA(I,L,J) and H5TC4G63AFR-xxA(I,L,J) are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device


and Ordering Information FEATURES • VDD=VDDQ=1.35V + 0.100 / – 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 and 11, 13 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both n [ … ]


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